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We are seeking a Senior Process Integration Engineer to own the integration of our whole product, from front-end wafer flows at our external fabs to reliable, high-yield assemblies working at cryogenic temperature. Reporting to our Chief of Engineering, you will be our technical counterpart at partner fabs, making sure each flow is right, step by step, and that the fabs deliver the quality our yield depends on. You will work hand in hand with our Process Development & Integration Engineer, who develops bumping, flip-chip and bonding, so that what the fab delivers can be assembled. And you will own the final question: is the integrated product working, and is it reliable?
About Isentroniq
At Isentroniq, we are building the future of computing, not in theory, but in hardware. We enable quantum computing at scale by developing superconducting circuit solutions that increase qubit count by more than 100x at fixed cost and infrastructure size.
We share knowledge openly, challenge ideas constructively, and stay focused on what matters. Our values (gritty ambition with humility, radical candor, surgical audacity, and self-accountable teamwork) are at the core of how we work and grow.
If you’re passionate about transformative innovation and ready to build the interconnects that make quantum computing at scale possible, join us.
Key Responsibilities
Own front-end integration at our external fabs. Act as our technical counterpart at partner fabs. Review process flows in depth, challenge assumptions and turn open questions into data-backed decisions. Expect regular on-site visits and process reviews.
Own integration of the whole product. Maintain the integrated flow from front-end steps through thinning, singulation and assembly to final test. Define the front-end to back-end interface (pad metallurgy and finish, wafer thickness, bow, alignment marks, handling frames) and the specifications and PCM that guarantee it.
Own yield. Build line-level and chip yield models, wafer maps and defect Paretos. Set quality targets with the fabs, and work with design on line redundancy so that mix-and-match stays simple.
Connect front-end, back-end and cryogenic data. Correlate PCM, inspection, assembly, electrical and mK test results. Find root causes, then feed corrections back to the fabs, to the back-end process and to our design rules.
Serve the back-end as your customer. Work daily with our Process Development & Integration Engineer on bumping, flip-chip and bonding. Understand how your front-end choices affect their processes, and use their data to improve yours.
Drive reliability and risk-based development. Run product-level FMEAs, fishbone analyses and DOEs. Define the qualification plan with our test team, including cryogenic cycling, and track risks such as delamination, undercut, resistance drift and impedance mismatch until they are closed.
Integrate across engineering teams. Work closely with our quantum, RF, mechanical and design engineers so that process choices meet 50 Ω impedance, thermalisation and mechanical requirements. Keep fab knowledge documented and retained in-house.
Who you are
We’re looking for an experienced integration engineer who goes deep into the data. You read a 100-step process flow and spot the wet etch that will undercut a 20 µm pad, then check the cryogenic data to prove it. You have owned product yield in a semiconductor or MEMS fab, and you know that high line yield at the fab is what keeps the product simple. You are comfortable with the ambiguity of deep tech, and equally at home in a process review, a cleanroom or a yield analysis.
Key Qualifications
Background in process integration. PhD or relevant Master's degree in materials science, physics, microelectronics or a related field, with at least 8 years of hands-on process integration in a semiconductor or MEMS fab, including ownership of product yield.
Expertise in front-end integration. You have owned multi-layer process flows (lithography, PVD, plating, wet and dry etch, lift-off, CMP, polymer dielectrics) and can judge the interactions between steps.
Yield and data analysis. Wafer maps, statistical yield modelling, SPC and correlation of data across test stages, using tools such as Python or JMP.
Solid back-end understanding. Working knowledge of bumping, flip-chip, bonding, thinning and dicing, enough to know how front-end choices affect assembly yield and reliability.
External fab management. You have run development with foundries or MEMS fabs: technical reviews, change control, deviations, yield and lead-time discussions.
Structured methods. Practical experience with PFMEA, DOE, 8D root-cause analysis and product qualification, and the habit of documenting.
Comfortable working hands-on in a cleanroom and at partner fabs, and willing to travel regularly.
Strong communication skills, clear and direct with partners and colleagues.
Communication proficiency in English
Bonus
Experience with superconducting materials (Nb, In, Sn-based solders) or cryogenic hardware down to mK temperatures.
Yield modelling for multi-channel or redundant products.
Experience with flexible substrates, thin or fragile wafers, polyimide-based flex or MEMS packaging.
Experience with thin-film resistors and RF or microwave products with impedance control.
Exposure to flip-chip, indium bump or laser-assisted bonding at product level.
Proficiency in French
Personal Attributes
You dive deep. You read flows line by line, ask the uncomfortable question at the fab, and go to the tool to see for yourself.
You own the product, not just the step. A front-end step that hurts back-end yield or cryogenic reliability is not good enough for you.
You are pragmatic. Working prototypes first, perfect processes second, with clear risk tracking in between.
You keep learning. You are as curious about cryogenic physics as you are experienced in process integration.
You embody radical candor. You raise problems early, with partners and internally, and welcome being challenged.
What We Offer
A unique opportunity to own the integration of a cutting-edge quantum hardware product, from front-end wafer flows to cryo-tested assemblies.
The chance to shape Isentroniq’s fab partnerships, yield strategy and integration methods from the ground up.
A collaborative, mission-driven culture with a focus on personal and professional growth.
Competitive salary and equity package.
Job Type
Permanent position
Location
St-Germain-en-Laye (FR)
Start Date
Now
Join us making quantum computing happen.
Please send your CV and a cover letter outlining your relevant experience and motivation.
Applications will be reviewed on a rolling basis, so we encourage early submissions.
